Today is day 2 at the Intel Developer Forum and with the first keynote out of the way, we can share a few short details about Ivy Bridge that we didn’t know before.  First, the transistor count is 1.48 billion – a hefty jump over Sandy Bridge that had less than 1 billion.

There was also mention of a new power management feature that will allow interrupts from other hardware devices to go to other cores than Core0, which it had ALWAYS done in the past. This means that it can route it to a core that is already awake and doing some work and not wake up a sleeping core unless necessary.

We also saw the Ivy Bridge processor running the HAWX 2 benchmark, now with support for DX11.

m12.jpg

If you look at the die image at the top of this post, you will also notice that it appears more of the die has been assigned to graphics performance than was allocated to it on Sandy Bridge.  Remember that on AMD’s Llano about 50% of the die dedicated to stream processors; it would appear that by adding support for DX11, nearly doubling performance and including required support for things like DirectCompute, Intel was forced to follow suit to some degree. 

Mooly laughed at press taking pictures of the die as he had purposely modified the image to hide some of the details or distort them to prevent precise measurements.  Still, it looks like about 33% of the new Ivy Bridge processor is dedicated to graphics and media.  This is good news for consumers, but potentially very bad news for the discrete GPU market in notebooks and low end PCs.

Finally, Mooly Eden ended with a brief look at future Ultrabooks that will be based on the Ivy Bridge processor.

m13.jpg

If you thought the current generation of Ultrabooks was sexy (as I do) then you will really like what is coming up next.